Field effect transistor with independently biased gates

ABSTRACT

A field effect transistor (FET) having at least two independently biased gates can provide uniform electric field in the channel region of the FET. The same AC voltage may be applied to each gate for modulating the FET. One of the gates is positioned closer to the channel region than the other gate. Such a FET allows tailoring the electric field in the channel region of the FET so that it is substantially uniform. The FET exhibits desirable performance characteristics, including having a constant transconductance.

RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.11/406,838, entitled “FIELD EFFECT TRANSISTOR WITH INDEPENDENTLY BIASEDGATES,” filed on Apr. 18, 2006, which is herein incorporated byreference in its entirety.

BACKGROUND OF INVENTION

Field effect transistors (FETs) are semiconductor devices used in a widevariety of electronics applications. A FET has three terminals: asource, a drain and a gate. During operation of the FET, current flowsbetween source and drain terminals through a channel region. The gateelectrode, positioned between the source and the drain, enables thecurrent through the FET to be controlled based on the strength of thesignal applied to the gate. The signal and bias present at the gate,source and drain determines the electric field profile in the channelregion between the source and the drain. The performance of the FET,e.g., factors such as current gain, carrier mobility, andtransconductance (g_(m)), are determined by the profile of the electricfield in the channel region.

In conventional FETs, the strength of the electric field varies over thelength of the channel, being typically weaker near the source andstronger near the drain (in depletion mode). A non-uniform field canlead to decreased performance of the FET, because electrons near thesource are accelerated slowly due to the relatively weak field in thisregion. Electrons near the drain may acquire too much energy due to therelatively strong field in this region, possibly causing damage to agate insulator. An excessively strong electric field in one region cancause mobility degradation, hot electrons and impact ionization, and cangenerate gate leakage. FIG. 1A illustrates an example of a conventionalmetal semiconductor field effect transistor (MESFET) having a source104, drain 106 and gate 108 formed on a substrate 102. FIG. 1B shows acurve 110 that illustrates an example of the magnitude of the electricfield E in the channel region while the MESFET is in depletion mode. Inthis example, the magnitude of the electric field is relatively weaknear the source and relatively strong near the drain. A non-uniformelectric field, such as that illustrated by curve 110, can lead todecreased carrier mobility, non-linearity and non-constanttransconductance.

Various techniques have been used to mitigate the effect of thenon-uniform electric field, such as using a lightly-doped drain, deltadoping of the channel, or using one or more field plates behind thegate. However, these methods lack flexibility to tailor the field inresponse to a range of operational voltages on the gate of the FET.Furthermore, no known field effect transistor provides constanttransconductance.

SUMMARY OF INVENTION

Embodiments of the invention relate to tailoring the electric field inthe channel region of a FET by appropriately positioning and biasing atleast two gates of the FET. In accordance with the invention, each ofthe gates may be biased independently. For example, the same AC voltagemay be applied to each gate, but each gate may biased at a different DCvoltage. In one aspect of the invention, the electric field may betailored by positioning one of the gates closer to the channel than theother gate. Using a FET with independently biased gates may enableproviding a uniform electric field in the channel region of the FET.Furthermore, such a device may exhibit substantially constanttransconductance, a high degree of linearity, and high breakdown, i.e.,Early voltage. Constant transconductance provides a high degree oflinearity, which can be particularly beneficial for amplifierapplications in which linearity across a broad range of gate voltages isdesirable.

One embodiment of the invention relates to a field effect transistorthat operates with substantially constant transconductance.

Another embodiment of the invention relates to a field effect transistorthat includes a channel region, a first gate biased at a first DCvoltage, and a second gate biased at a second DC voltage and positionedfarther from the channel region than the first gate.

A further embodiment of the invention relates to a field effecttransistor that includes a source, a drain and a semiconductor region.The field effect transistor also includes a first gate biased at a firstDC voltage and contacting the semiconductor region. The field effecttransistor further includes a second gate biased at a second DC voltagelower than the first DC voltage. The second gate is separated from thesemiconductor region by an insulating region.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings are not intended to be drawn to scale. In thedrawings, each identical or nearly identical component that isillustrated in various figures is represented by a like numeral. Forpurposes of clarity, not every component may be labeled in everydrawing. In the drawings:

FIG. 1A is a cross-section of a conventional MESFET;

FIG. 1B is a diagram showing a curve that illustrates the magnitude ofthe electric field in the channel region of the MESFET illustrated inFIG. 1A;

FIG. 2 is a cross-section of a pseudomorphic high-electron-mobilitytransistor (pHEMT) according to one embodiment of the invention;

FIG. 3 is a diagram illustrating an example of a cross-section of apHEMT having three gates, according to another embodiment of theinvention;

FIG. 4 is a cross-section of a metal-oxide-semiconductor field effecttransistor (MOSFET), according to another embodiment of the invention;

FIG. 5 is a cross-section of a pHEMT, including an overlapping gatestructure, according to another embodiment of the invention; and

FIG. 6 is a diagram illustrating examples of curves that represent thetransconductance of FETs for a range of gate voltages.

DETAILED DESCRIPTION

In accordance with some embodiments of the invention, a FET having atleast two independently biased gates enables tailoring the electricfield in the channel region of the FET. One of the gates may bepositioned closer to the channel than the other gate. Using such aconfiguration, the electric field may be tailored so that it issubstantially uniform in the channel region, which can improve theperformance of the FET. For example, the FET can achieve substantiallyconstant transconductance. Embodiments of the invention may be useful ina variety of amplifiers, mixers, switches or any other suitablecircuits.

FIG. 2 is a cross-section of a pseudomorphic high-electron-mobilitytransistor (pHEMT) according to one embodiment of the invention. In thisembodiment, pHEMT 200 includes a source 204, drain 208, a first gate 205and a second gate 206. Source 204, drain 208, first gate 205 and secondgate 206 may be metallizations formed of any suitable material, e.g., ametal such as aluminum. Source 204, drain 208, first gate 205 and secondgate 206 may be separated by an insulating region 210 which may be anysuitable insulating material such as silicon nitride or silicon dioxide.Insulating region 210 may include one material or a combination ofmaterials, as the invention is not limited in this respect. In thisembodiment, pHEMT 200 includes a first semiconductor layer 212, e.g.,gallium arsenide (GaAs), a second semiconductor layer 214, e.g.,aluminum gallium arsenide (AlGaAs), a channel region 216, e.g., indiumgallium arsenide (InGaAs), and a substrate 218. The materials describedherein are provided merely by way of illustration, as the invention isnot limited to any particular types of materials.

First gate 205 may form a Schottky contact with first semiconductorlayer 212, and may be closer to source 204 than second gate 206. Secondgate 206 may be separated from first semiconductor layer 212 byinsulating region 210, and may be closer to drain 208 than first gate205. In this embodiment, second gate 206 may be wider than first gate205. First gate 205 and second gate 206 may be separated by a portion ofinsulating region 210. In some embodiments, second gate 206 may beseparated from first semiconductor layer 212 by a distance of less than1000 angstroms, e.g., 100 angstroms. Positioning second gate 206 within1000 angstroms of first semiconductor layer 212 enhances the control ofthe electric field in the channel region.

During operation of pHEMT 200, electrons may be conducted through InGaAschannel region 216 between the source 204 and drain 208 in response to agate signal applied to first gate 205 and second gate 206. In accordancewith the invention, the first gate 205 and the second gate 206 may bebiased at different DC levels. In particular, the gates may be biasedsuch that the DC voltage of first gate 205 is greater than the voltageof second gate 206 (V_(g1, DC)>V_(g2, DC)). Such a biasing configurationmay be used for depletion mode FETs, however, for enhancement mode FETsthe biasing configuration may be the opposite (V_(g1, DC)<V_(g2, DC)).

First gate 205 and second gate 206 may have the same AC voltage appliedthereto for modulating the conduction of pHEMT 200. Alternatively, theAC signal may be applied to the two gates in a magnitude ratio that isthe same as the ratio of their respective bias voltages, to enhancelinearity. However, providing the same AC voltage to both first gate 205and second gate 206 can reduce the effect of a parasitic capacitancethat couples first gate 205 to second gate 206. However, the same ACvoltage need not necessarily be applied to both first gate 205 andsecond gate 206. For example, an AC voltage be applied to only one ofthe two gates. Such a mode of operation may simplify the design of acircuit that supplies the AC voltage, and may be suitable for relativelylow frequencies of operation. An AC signal may be applied to one or moregates in any suitable way, as the invention is not limited in thisrespect.

The Applicants have appreciated that using at least two independentlybiased gates in such a configuration enables tailoring the electricfield in channel region 216 so that it is substantially uniform. As aresult, such a FET may exhibit substantially constant transconductanceover a wider range of gate voltages than was previously possible.Furthermore, linearity of the FET and electron mobility may be improved.

As discussed above, FIG. 2 illustrates an example of a pHEMT 200 thathas two gates 205 and 206. However, more than two gates may be used, asthe invention is not limited in this respect. Providing a transistorwith more than two gates may facilitate achieving a uniform electricfield in the channel region. For example, three or more gates may beused, and each gate may be biased independently of the other gates.

FIG. 3 is a cross-section of a pHEMT 300 having three gates, accordingto another embodiment of the invention. In this embodiment, pHEMT 300includes three gates 205, 306 and 307, each of which may be biased atdifferent DC voltages. For example, the gates may be biased such thatthe voltage of first gate 205 is greater than the voltage of second gate306, and the voltage of second gate 306 is greater than that of thirdgate 307 (V_(g1, DC)>V_(g2, DC)>V_(g3, DC)). Such a biasingconfiguration may be used for depletion mode FETs, however, forenhancement mode FETs the biasing configuration may be the opposite(V_(g1, DC)<V_(g2, DC)<V_(g3, DC)).

Each of the three gates 205, 306 and 307 may have the same AC controlsignal applied thereto for modulating pHEMT 300. However, the same ACvoltage need not necessarily be applied to each gate. For example, an ACvoltage be applied to only one or two of the three gates. Such a mode ofoperation may simplify the design of a circuit that supplies the ACvoltage, and may be suitable for relatively low frequencies ofoperation. An AC signal may be applied to one or more gates in anysuitable way, as the invention is not limited in this respect.Furthermore, embodiments of the invention may have any suitable numberof gates.

The invention is not limited as to the particular materials used for thevarious regions of the FET. The semiconductor regions may be anysuitable semiconductor regions, such as silicon, germanium, galliumarsenide, gallium nitride, etc., as the invention is not limited in thisrespect. Furthermore, the gate, source and drain metallizations may beformed of any suitable conductive material, e.g., a metal such asaluminum. As discussed above, the insulating regions may be formed ofany suitable insulating material, e.g., silicon nitride or silicondioxide, or a combination of materials.

FIGS. 2 and 3 illustrate examples of pHEMTs according to someembodiments of the invention. However, it should be appreciated thepresent invention is not limited to pHEMTs, but may be applied to anysuitable type of FET, e.g., MOSFETs or MESFETs. Accordingly, anotherembodiment of the invention will now be described that illustrates howaspects of the invention may be implemented in metal-oxide-semiconductor(MOS) technology.

FIG. 4 is a cross-section of a metal-oxide-semiconductor field effecttransistor 400 (MOSFET), according to another embodiment of theinvention. MOSFET 400 may include a source 204, drain 208, first gate405, second gate 406, insulating region 210, N doped semiconductorregions 412 and 413, and P doped semiconductor regions 414 and 415.Semiconductor regions 412-415 may be regions of any suitablesemiconductor material, e.g., silicon. Source 204, drain 208, first gate405 and second gate 406 may be metallizations formed of any suitablematerial, e.g., polysilicon, or a metal such as aluminum. Source 204,drain 208, first gate 405 and second gate 406 may be separated by aninsulating region 210 which may be any suitable insulating material,such as silicon nitride or silicon dioxide. Although FIG. 4 illustratesan example of an N-channel MOSFET, it should be appreciated that theinvention is not limited in this respect, as aspects of the inventionmay be implemented in a P-channel MOSFET or any other suitable FET.

First gate 405 and second gate 406 may be separated from semiconductorregions 412-415 by insulation region 210. First gate 405 may bepositioned closer to source 204 than second gate 406, which may bepositioned closer to drain 208 than first gate 405. In this embodiment,first gate 405 is positioned closer to the channel region of MOSFET 400,e.g., a portion of semiconductor region 414, than second gate 406.Positioning first gate 405 closer to the region 414 than second gate 406allows shaping the electric field in the channel region so that issubstantially uniform.

FIG. 5 is a cross-section of a pHEMT 500 according to another embodimentof the invention. In this embodiment, second gate 506 includes a portionthat is above first gate 205 and a portion that is on one side of firstgate 205. Such an overlapping gate structure controls the parasiticcapacitance between first gate 205 and second gate 506 by controllingthe thickness of insulating region 210 between first gate 205 and secondgate 506. The thickness of the insulating region 210 between first gate205 and second gate 506 may be, for example, approximately 100angstroms. As discussed above, first gate 205 may be biased at a higherDC voltage than second gate 506, yet both first gate 205 and second gate506 may have the same AC voltage applied thereto for modulating pHEMT500. As one example, first gate 205 may be biased approximately 0.6volts higher than second gate 506.

By way of example, FIG. 5 illustrates dimensions of various features ofpHEMT 500 according to one embodiment of the invention. In thisembodiment, the first gate 205 and the second gate 506 may be positionedapproximately 1.5 μm from source 204 in the lateral dimension, e.g.,parallel to a wafer surface. A portion of the second gate may bepositioned approximately 1.5 μm from drain 208 in the lateral dimension.First gate 205 may extend approximately 0.5 μm in the lateral dimension,and second gate 506 may extend approximately 2.0 μm in the lateraldimension. These dimensions are provided merely by way of example, andare not intended to be limiting. One of ordinary skill in the art wouldappreciate that the FET may be of any suitable size, and that thedimensions may be scaled accordingly. However, different dimensionsand/or relative sizes between dimensions may be used, as the inventionis not limited in this respect. For larger devices, the differencebetween the DC bias voltages on first gate 205 and second gate 506 maybe increased to maintain a uniform electric field in the channel region.

As discussed above, some embodiments of the invention are directed to aFET that provides substantially constant transconductance. As usedherein, transconductance is the ratio of the change in drain current tothe change in gate-source voltage of the FET. Substantially constanttransconductance means that the transconductance of the FET does notvary substantially over a range of gate voltages. Furthermore, thetransconductance can be substantially constant across a range offrequencies.

FIG. 6 is a diagram illustrating examples of curves 601 and 602 thatrepresent the transconductance of two different FETs for a range of gatevoltages. Curve 601 represents the transconductance for a conventionalFET that uses a field plate in an attempt to provide a uniform electricfield in the channel region. Curve 601 illustrates that thetransconductance of this conventional FET reaches nearly 300 mS/mm,before dropping rapidly at approximately 0.3 V of gate bias. Such anon-constant transconductance may lead to non-linearity, e.g., somevoltages being amplified at a higher level than other voltages.

Curve 602 illustrates the modeled transconductance that may be achievedfor a FET according to the embodiment of the invention illustrated inFIG. 5. Curve 602 shows that the transconductance of the FET does notvary significantly (e.g., less than 25 mS/mm peak-to-peak) over therange of −0.6 V to 1.0 V gate voltage. Such a substantially constanttransconductance provides improved performance and substantially linearoperation of the FET over this range of operating voltages on the gate.

In the above-described embodiments, gates were positioned and biased toincrease the electrical field near the source and decrease theelectrical field near the drain, so that the electrical field would besubstantially uniform throughout the channel. However, in somecircumstances, the electric field may be large near the source and smallnear the drain. Such a situation may arise, for example, for a MESFET inenhancement mode. In such a situation, obtaining a uniform electricfield may require decreasing the electric field near the source andincreasing the electric field near the drain. To achieve a uniformelectric field in such a scenario, the orientation of theabove-described embodiments may be altered such that the positions ofthe drain and the source are reversed, for example.

Having thus described several aspects of at least one embodiment of theinvention, it is to be appreciated various alterations, modifications,and improvements will readily occur to those skilled in the art. Suchalterations, modifications, and improvements are intended to be part ofthis disclosure, and are intended to be within the spirit and scope ofthe invention. Accordingly, the foregoing description and drawings areby way of example only.

1. A field effect transistor, comprising: a channel region; a first gatebiased at a first DC voltage; and a second gate biased at a second DCvoltage and positioned farther from the channel region than the firstgate.
 2. The field effect transistor of claim 1, wherein the first DCvoltage is greater than the second DC voltage.
 3. The field effecttransistor of claim 1, further comprising: a source; and a drain;wherein the first gate is positioned closer to the source than to thedrain.
 4. The field effect transistor of claim 1, further comprising: asemiconductor region; wherein the first gate forms a Schottky contactwith the semiconductor region.
 5. The field effect transistor of claim1, further comprising: a semiconductor region; wherein the second gateis positioned within approximately 1000 angstroms of the semiconductorregion.
 6. The field effect transistor of claim 5, wherein the secondgate is positioned within approximately 100 angstroms of thesemiconductor region.
 7. The field effect transistor of claim 1, whereinthe field effect transistor is a high-electron-mobility transistor. 8.The field effect transistor of claim 1, wherein the field effecttransistor is a metal-oxide-semiconductor field effect transistor.
 9. Afield effect transistor, comprising: a source; a drain; a semiconductorregion; a first gate biased at a first DC voltage and contacting thesemiconductor region; and a second gate biased at a second DC voltagelower than the first DC voltage, the second gate being separated fromthe semiconductor region by an insulating region.
 10. The field effecttransistor of claim 9, wherein the field effect transistor is ahigh-electron-mobility transistor.
 11. The field effect transistor ofclaim 9, wherein the second gate is separated from the semiconductorregion by less than approximately 1000 angstroms of the insulatingregion.
 12. The field effect transistor of claim 11, wherein the secondgate is separated from the semiconductor region by approximately 100angstroms or less of the insulating region.
 13. The field effecttransistor of claim 9, wherein at least a portion of the second gate ispositioned above the first gate.
 14. The field effect transistor ofclaim 9, wherein the first gate is positioned closer to the source thanthe second gate.
 15. The field effect transistor of claim 9, wherein thesecond gate is positioned closer to the drain than the first gate. 16.The field effect transistor of claim 9, wherein the first gate isseparated from both the first gate and the semiconductor region by asame distance of approximately 100 angstroms or less of the insulatingregion.
 17. The field effect transistor of claim 9, further comprising athird gate biased at a third DC voltage and separated from thesemiconductor region by an insulating region.
 18. The field effecttransistor of claim 1, wherein the field effect transistor operates withsubstantially constant transconductance.
 19. The field effect transistorof claim 18, wherein the substantially constant transconductance variesby no more than 25 mS/mm over a range of gate bias voltages spanning atleast one volt.
 20. The field effect transistor of claim 9, wherein thefield effect transistor operates with substantially constanttransconductance.